HFETs (Heterojunction Field Effect Transistors) have found use in mobile telephones and other communications systems and devices. Such devices have often been used in depletion mode, thus requiring the application of a positive bias to the drain electrode and a negative bias to the gate electrode. This, in turn, has required the presence of a positive and negative power source, resulting in an increase in the size and weight of the system or device. Consequently, it has become desirable in these applications to replace the depletion mode HFET with an enhancement mode HFET, which does not require the application of a negative bias to the gate electrode or the accompanying devices required to achieve that bias.
FIG. 1 shows a simplified cross-sectional view of a known enhancement mode HFET. The device 1 shown therein is formed on a wafer 3 and includes a buffer layer 5 comprising GaAs which is formed on the upper surface of the wafer. An InGaAs channel layer 7 is formed on the buffer layer, an AlGaAs barrier layer 9 (so called because the bandgap of AlGaAs is larger than the bandgap of either GaAs or InGaAs) is formed on the channel layer, and a cap layer 11 made out of a material such as gallium arsenide (GaAs) is formed on the barrier layer. Source 13 and drain 15 areas are formed by ion implantation through the cap layer and extend through the cap layer, the barrier layer, and the channel layer and partially into the buffer layer. A source contact 17 and a drain contact 19 are disposed above the channel layer. A dielectric layer 21 is disposed over the cap layer and the source and drain contacts. The resulting structure is then covered with a material such as tetraethyl orthosilicate (TEOS) 27. An opening is etched through the TEOS layer, dielectric layer and the cap layer, and metal is deposited in the opening to form a gate 25.
While enhancement mode HFETs of the type depicted in FIG. 1 have many desirable properties, these devices are frequently found to exhibit a forward turn-on voltage of the gate diode (VON) that is unexpectedly lower than the design value. Many of these devices are found to be prone to excessive current leakage and poor gate properties, as well as excessive contact and access resistances. There is thus a need in the art for methods for making enhancement mode HFETs that exhibit a VON comparable to the design value, and that have improved gate properties and minimized contact and access resistances, but do not result in excessive current leakage. These and other needs are met by the devices and methodologies disclosed herein.